Riviera-PRO in ISE, Riviera-PRO in VivadoĬompile simulation libraries as explained in the previous section Compiling Xilinx Simulation Libraries for Aldec.
Alternatively, you can start Aldec Active-HDL or Riviera-PRO and run an RTL/Behavioral, Netlist, or Timing simulation directly from the Xilinx graphical environment refer to the following application notes for details on how to set Aldec as default simulator: The following sections ( Running RTL/Behavioral Simulation, Running Netlist Simulation, Running Timing Simulation) provide a quick reference for running a simulation outside of Xilinx’s GUI.
NOTE: If you use a VHDL-only Active-HDL or Riviera-PRO configuration, you must download the SECUREIP library from Aldec website since Xilinx’s SECUREIP contains sources in Verilog, Aldec provides a special watermarked version of the SECUREIP to enable simulation with VHDL-only license refer to Language Neutral Libraries with Xilinx application note for more details. When this command is run with a project open, the tool will use the device family, target language, and library settings specified by the project as the default values, rather than the default settings of the command the default settings can be overridden by specifying the necessary options when the command is run. Use the compile_simlib Tcl command in the Vivado Design Suite Tcl Console for compiling Xilinx HDL-based simulation libraries for Aldec. There are several ways to compile and attach Xilinx simulation libraries, depending on Xilinx tool you use: Table 2: Xilinx Libraries Required in Simulation PointsĬompiling Xilinx Simulation Libraries for Aldec
Table 2 categorizes the libraries by simulation points. (There are different gate-level cells in pre- and post-implementation netlists). You must specify different simulation libraries according to the simulation points. Used for functional and timing simulation of complex FPGA components, such as PCIe® IP, Gigabit Transiever Used for simulating timing simulation netlists produced after synthesis or implementation. Used during RTL Behavioral simulation for designs containing certain cores created by the Xilinx IP catalog Used during functional simulation and contains macro descriptions for selective device primitivesĪn optional library that can be used during RTL behavioral simulation to speed up simulation runtime Used during functional simulation and contains descriptions for all the device primitives, or lowest-level building blocks ( Table 1 lists Xilinx simulation libraries).
When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation. It is one of the first steps after design entry and one of the last steps after implementation as part of the verifying the end functionality and performance of the design.įigure 1: Xilinx Simulation Flow Xilinx Simulation Libraries Overview Simulation can be applied at several points in the design flow ( Figure 1). UG626 Synthesis and Simulation Design Guide (ISE users) UG900 Vivado™ Design Suite Logic Simulation User’s Guide (Vivado users)
This application note provides a quick overview of Xilinx®-targeted simulation flow based on Aldec’s design and verification environments, Active-HDL™ or Riviera-PRO™ detailed information can be found in the following Xilinx documents:
Simulating a Design with Xilinx Libraries (UNISIM, UNIMACRO, XILINXCORELIB, SIMPRIMS, SECUREIP)